1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to cell based integrated circuit layout architecture that is configurable as a logic device or a single/dual port memory cell using no more than two configurable cells.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
An integrated circuit generally comprises the interconnection of various circuit elements. Those circuit elements include transistors, resistors, capacitors, logic gates, flip-flops, registers, etc. In order to achieve functionality, the various circuit elements must be interconnected with attention given to where those elements are relative to each other. For example, performance of the integrated circuit is affected by where the elements are connected, and the interconnect length between elements. Optimal performance of circuit elements upon the integrated circuit substrate is generally dictated by the “layout” of the integrated circuit.
Layout considerations oftentimes depend on a tradeoff between performance and cost. In an application-specific integrated circuit (ASIC), placement of elements and the interconnection therebetween is unique to that particular integrated circuit design. That is, layout is performed on a chip-by-chip basis and cannot be easily modified whenever a design change is needed for that particular product. An ASIC thereby enjoys the benefits of high performance, but also has a fairly high non-recurring expense each time a design change is needed.
At the opposite end of the spectrum from ASIC design is the more versatile gate array concept. A gate array can be designed into a base pattern and thereafter fabricated into an integrated circuit for customer-specific functional requirements. A typical gate array consists of pre-designed circuit units or cells that are wired together to rapidly implement the final integrated circuit functionality. The pre-designed circuit elements are called basic cells that, when interconnected, becomes the macro cell building blocks for the final integrated circuit product. The functionality of the final integrated circuit is thereby dictated by the interconnection of the macro cells, and that interconnection can vary depending on any changes in functionality.
Gate array technology allows the pre-designed circuit unit to be fixed and need not change from one final circuit design to the next. Placement of interconnection that can vary depending on the final result thereby adds configurability (or reconfigurability) to the gate array design. Thus, the concept of “fixed” and “variable” cell design applies to gate array technology to afford a lower non-recurring expense if any design change is needed. The design change can be implemented on the variable fabrication layers, yet the fixed layers will remain the same.
Gate array technology generally allows changes to be made in the field to implement what is known as field-programmable gate arrays (FPGAs). FPGAs unfortunately have lower performance and higher power consumption relative to ASIC designs, yet enjoy a lower non-recurring expense. A special form of ASIC, known as structured ASIC, serve somewhat as a compromise between FPGAs and standard ASICs.
Similar to gate arrays, structured ASICs implement basic cells that are interconnected to form circuit elements. However, structured ASICs are not programmed in the field as in FPGAs, nor do structured ASICs consist of pre-designed circuit elements (e.g., logic gates, flip-flops, registers, etc.) that are wired together to form the integrated circuit. Instead, structured ASIC technology utilizes cells that may contain one or more transistors that are customized by connecting a transistor within one cell to possibly several transistors in another cell, yet all cells of the fixed layers look alike. The variable layers and, specifically, the variable interconnect layers, provide reconfigurability to the structured ASIC.
While structured ASICs have better performance and lower power consumption than gate arrays, and have a lower non-recurring expense relative to standard ASICs, structured ASICs nonetheless have limitations as to what type of integrated circuit they can form. With the advent of greater integration and the use of system-on-chip (SoC) technology, modern design places as many subsystems on the integrated circuit as possible. One such popular subsystem includes semiconductor memory. Conventional structured ASICs are generally limited to fixed layers of transistors that are thereafter interconnected through variable layers to form logic circuits, such as NAND gates, NOR gates, etc. Unfortunately, modern SoCs mandate that the final integrated circuit contain more than just logic gates.
It would be desirable to implement a structured ASIC that can be reconfigured as logic gates, registers, flip-flops, and all other logic circuitry, as well as or in addition to memory. It would also be desirable to introduce a structured ASIC that can achieve a single port or dual port memory cell using a minimum number of ASIC cells. If the final memory density is to be feasible, the desired circuit layout architecture must contain the necessary building blocks for logic as well as memory within a minimum number of layout cells that repeat as a fabric or array across the integrated circuit.